1. Field of the Invention
The present invention relates to multiplexers and more particularly to a multiplexer including 2.sup.q+1 input signals, where 9 is an integer and greater or equal one each input signal out of phase with respect to the other input signals by 360.degree./2.sup.q+1 and which input signals are successively selected according to increasing phase delays.
2. Discussion of the Related Art
A multiplexer receiving such signals is particularly useful to fabricate a fast operating divider by 2.sup.m+ 1/2, such as the divider described in U.S. Pat. No. 5,189,685.
FIG. 1 schematically represents the divider by 2.sup.m+ 1/2 of the above-mentioned patent application. Such divider includes a multiplexer 10 receiving for example 8 input signals S1-S8 provided by a 4-bit counter 12 of the Johnson-type, whose particularity is to provide identical signals, each signal being out of phase with respect to the other signals by a constant value; in this example, by 360.degree./8. Counter 12 receives signal F to be divided. The output 01 of multiplexer 10 is provided to a divider by 2.sup.n, where "n" is an integer 14, whose output provides the circuit output signal 0. Signal 0 is further looped back through a control circuit 16 of multiplexer 10. The control circuit 16 is operable to change the selection of multiplexer 10 at each predetermined edge of signal 0. Multiplexer 10 is controlled to successively provide at each switching the input signals in the order of increasing phase delays. In the example of FIG. 1, a particularly fast divider by 2.sup.n+2 +1/2 is provided.
Hereinafter, Si designates the current signal selected in multiplexer 10, and Si+1 designates the next signal to be selected (i or i+1=1, 2 . . . 8).
FIG. 2 is a timing diagram of the signals in FIG. !in three different situations delineated by two vertical dotted lines. FIG. 2 shows the signal F to be divided; signals Si and Si+1; output signal 0 of the divider by 2.sup.m+ 1/2 having three different delay values, T.sub.1, T.sub.2, T.sub.3 ; and output signal 01 of multiplexer 10. Signals Si and Si+1 are identical and have a 50% duty cycle. Signal Si+1 has a phase lag with respect to signal Si corresponding to one half-period of signal F (which corresponds to 1/8 of the period of signal Si or Si+1, or still to 360.degree. /8).
In FIG. 2 are represented at times t.sub.1, t.sub.2 and t.sub.3 three rising edges of signal 0, each of which causes switching of multiplexer 70 from signal Si to signal Si+1. The aim of switching from one signal to the next one is to "swallow" a half-period of signal F, which provides term 1/2 in the division ratio 2.sup.m+ 1/2.
Switchings occur aft times that depend on the delay introduced by divider 14, the delay of the control circuit being here neglected for the sake of simplification. This delay corresponds to the switching delay of n latches if divider 74 is a divider by 2n. Ideally, the switching operations occur at times analogous to times t.sub.1 and t.sub.2 when signals Si and Si+1 have a same logic state. In this case, the current phase (high state at time t.sub.1 and low state at time t.sub.2) of signal 01 is prolonged by one half-period of signal F.
Time t.sub.3 corresponds to a switching time that is to be avoided. Switching occurs while signals Si and Si+1 are at different logic states. In FIG. 2, time t.sub.3 occurs when signal Si is high while signal Si+1 is not yet high. The output signal 01 of multiplexer 70 has, between time t.sub.3 and the next rising edge of signal Si+1, an undesirable low state. Then, signal 01 has an additional edge causing erroneous counting by divider 14.
In a given technology, the delay introduced in divider 14 is approximately known. The circuit is designed so that the switching operations of multiplexer 10 occur when the current signal Si and the next signal Si+1 to be selected have the same state. However, if the input frequency F varies, the switching time slides, for example, from a situation corresponding to time t.sub.2 to an inappropriate situation corresponding to time t.sub.3. Therefore, the divider of FIG. 1 can operate within a limited frequency range only.